One example of a semiconductor device provided with a semiconductor layer having a region configured at consistent widths is a nonvolatile semiconductor storage device such as a flash memory. The nonvolatile semiconductor device is configured by compartments of regions constituted by a memory cell region configured by a plurality of memory cells each provided with a floating gate electrode; and a peripheral circuit region configured by peripheral circuits that drive the memory cells of the memory cell region.
The memory cell region of the nonvolatile semiconductor storage device includes a region where the memory cells are actually formed (hereinafter referred to as the cell array forming region). In the cell array forming region, the active area and the floating gate electrode layer are disposed at predetermined consistent widths in a predetermined direction parallel to the surface of the semiconductor substrate. Hence, multiple memory cells having desired characteristics are formed in the memory cell region to achieve integration and shrinking of the memory cells.
On the other hand, provided at the end of the of the memory cell region is a guard ring region (cell array end region) having increased width which is provided in the element isolation region. The cell array forming region, being electrically connected to a power supply terminal, and the like, is provided with a well contact region for establishing electrical connection with a well provided in the semiconductor substrate. The guard ring region and the well contact region need to be designed to have greater widths compared to the widths of the active area and the floating gate electrode layer of the cell array forming region in order to respectively retain their desired electrical characteristics. U.S. Pat. No. 6,521,941 discloses a nonvolatile semiconductor storage device provided with a dummy gate electrode structure on the gate electrode in the peripheral circuit region.
In the description given hereinafter, the active area and the floating gate electrode layer forming region of the cell array forming region are identified as a first region (cell array forming region) and the region (guard ring region and well contact region, and the like) having greater width compared to the first region is identified as a second region. In order to secure insulation from other regions or to obtain contact area, consistent width cannot be obtained at the boundary between the first region and the second region and in the proximity of the boundary, as far as design is concerned.
The lack of consistency in width results in reduction in exposure resolution of photolithography process executed during the device manufacturing process. Thus, the floating gate electrode layer in the proximity of the boundary region cannot be configured in a form having the desired characteristics. Therefore it is necessary to maintain consistency in the width dimension with minimum variation in the proximity of the boundary region.
Under such circumstances, there are some cases where substantially the same structure applied for the cell array forming region is employed for the structure formed over the surface of the semiconductor substrate of the second region as well. In other words, a dummy gate electrode layer corresponding to the floating gate electrode layer of the first region is provided in the second region. However, under such configuration, high electrical field applied to the floating gate electrode layer of the first region for write and erase operation results in application of high electrical field to the dummy gate electrode layer of the second region.
Consequently, insulation capacity of the insulation film becomes more prone to deteriorate by application of high electrical field in the second region because of its lower coupling ratio compared to the first region. Deterioration in insulation capacity of the insulating film leads to defects in electrical components of the device. Especially in the light of recent demand for thinner inter-gate insulating films, employing the inter-gate insulating film of the first region as it is to serve as an insulating film for covering the dummy gate electrode provides risk factors leading to destruction of the insulating film and the degradation in insulating capacity.